The present invention relates to the field of the integrated circuit fabrication. More specifically, the invention provides a technique of fabricating a nonvolatile memory device for an integrated circuit, where the nonvolatile memory device has reduced substrate hot electrons.
Interconnect is a fundamental component of integrated circuits. Interconnect is used to couple the elements, components, circuits, and signals in an electronic system together in order to perform functions. For example, interconnect is used to supply power to the electronic components. Interconnect is also used to implement analog and digital functions in electronic systems. Interconnect, especially programmable or configurable interconnect, is especially useful in particular applications, such as, but not limited to, programmable logic devices (PLDs) where it is desirable for interconnections to be programmably determined. Other applications may include microprocessors, memories, and application specific integrated circuits (ASICs), to name a few.
PLDs are well known to those in the electronic art. Programmable logic devices are commonly referred to as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs, PLDs, EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known, Classic(trademark), and MAX(copyright) 5000, MAX(copyright) 7000, and FLEX(copyright) 8000 EPLDs made by Altera Corp.
PLDs are generally known in which many logic array blocks (LABs) are provided in a two-dimensional array. LABs contain a number of individual programmable logic elements (LEs) which provide relatively elementary logic functions such as NAND, NOR, and exclusive OR. The functions within LABs and LEs may be implemented using function generators, lookup tables, AND-OR arrays, product terms, multiplexers, and a multitude of other techniques. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the LABs and LEs.
The configuration information of the LABs, LEs, and interconnections between these logical elements have been typically stored in memory cells. Memory cells may be used to programmably control the composition, configuration, and arrangements of logic array blocks (LABs) and logic elements (LEs) and also the interconnections between these logic array blocks and logic elements.
Many different memory cell technologies may be used including dynamic random access memory (DRAM), static random access memory (SRAM), erasable-programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), Flash EEPROM memory, and antifuse, among others. Typically, the technology used to store the configuration information of the PLD should be compact, power efficient, programmable and nonvolatile, require little additional programming circuitry overhead, and generally provide enhancements to the performance and features of PLD logic modules and interconnections.
While PLDs have met with substantial success, such devices also meet with certain limitations. There is a continuing need for programmable logic integrated circuits with greater capacity, density, functionality, and performance. Resulting from the continued scaling and shrinking of semiconductor device geometries which are used to form integrated circuits (also known as xe2x80x9cchipsxe2x80x9d), integrated circuits have progressively become smaller and denser. For programmable logic, it becomes possible to put greater numbers of programmable logic elements onto one integrated circuit. As the number of elements increases, it becomes increasingly important to improve the techniques and architectures used for programmably interconnecting the elements and routing signals between the logic blocks. Also as PLDs increase in size and complexity, greater numbers of memory cells are required to hold the configuration information of the logical elements and many programmable interconnections are needed.
This produces a need to implement logic functions more efficiently and to improve the portion of the device which is devoted to interconnecting individual logic modules. The provision of additional or alternative techniques for implementing the programmable interconnection between the logic modules should have benefits sufficient to justify the additional circuitry and programming complexity. The capacity, complexity, and performance of PLDs are determined in a large part by the techniques used to implement the logic elements and interconnections. The techniques used to implement the logic and programmable interconnect should have improved operating characteristics such as lower power consumption, nonvolatility, greater device longevity, improved data retention, better transient performance, and superior voltage and current attributes, as well as many other characteristics. Furthermore, the technology should facilitate manufacturability and testability.
As can be seen, improved techniques for implementing programmable interconnect are needed, especially for implementing the logic and interconnects in a programmable integrated circuit.
The invention provides a technique of fabricating a nonvolatile device with a low doping region that helps reduce substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this helps improve the reliability and longevity of the nonvolatile device.
In an embodiment, the invention is a method of fabricating a nonvolatile device including forming a floating gate of the nonvolatile device on a substrate. And a low doping region is formed in the substrate. The low doping region has a lower doping concentration than in the substrate. The low doping region reduces substrate hot electrons. In a specific implementation, the low doping region has a doping concentration of about 3xc3x971016 cmxe2x88x923. The low doping region may be doped using boron. A depth of the low doping region is about 0.5 microns. Source and drain regions for the nonvolatile device may have a junction depth of from about 0.1 microns to about 0.3 microns. The low doping region may be positioned beneath the floating gate and between the source and drain regions. A doping concentration of the substrate may be about 1xc3x971017 cmxe2x88x923. A depth of the low doping region may be greater than an expected depletion region for the nonvolatile device.
The method may further include implanting an adjust implant to be located beneath the floating gate and at or near a surface of the substrate, where a doping concentration of the adjust implant is about 6xc3x971011 cmxe2x88x922. To form the low doping region, this may involve doping the substrate more heavily than a target doping level for the low doping region. And then, the low doping of the substrate is counterdoped to obtain the target doping level.
In another embodiment, the invention is a method of forming a nonvolatile, floating gate transistor including forming a gate oxide layer on a substrate. A floating gate is formed on the gate oxide layer. Two diffusion regions are formed in the substrate along opposite edges of the floating gate. A low doping region is formed in the substrate, beneath the gate oxide and between the diffusion regions, where the low doping region has a lower doping concentration than the substrate. The low doping region reduces substrate hot electrons. The method may further include implanting a threshold voltage adjust implant beneath the gate oxide and at or near a surface of the substrate. The method may further include doping the substrate more heavily than a target doping level for the low doping region. Then, the low doping of the substrate is counterdoped to obtain the target doping level. The method may further include forming a gate oxide beneath the floating gate and on the substrate, forming a source region in the substrate, and forming a drain region in the substrate.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.